module Pc (
    input [31:0] npc,
    input clk,
    input rst,
    input stall,
    output reg [31:0] pc

);
   
    
    
    parameter default_pc = 32'h00400000;
    initial begin
        pc <= default_pc;
            
    end
    always @(posedge clk or posedge rst) begin
        if(clk)
        begin
        if(!stall)
            pc <= npc;
        end
        else
        begin
             pc <= default_pc; 
             $display("reset");
        end
               
    end
endmodule //pc